Project - | Project Ananth using Open POWER ISA |
Objective | The goal of the project is to make a indegenious processor core in India .. |
Outcomes | "ANANTH 1.0" is a fabless SoC (System on Chip) going to be designed and developed at VLSI labs, Electronics and Communication Engineering Department, JNTUA college of engineering, Anantapur.
This is indigenously developed fabless SoC for academic R&D purposes.
The applications developed in high level languages (C) shall be given as an input to the processor core post compilation of this application on power SDK (Software Development Kit) which yields a binary / ELF (Executable and Linking Format) of the application.
The SoC is designed with the following interfaces and interconnects:
AMBA AXI4
SPI
I2C
ETHERNET
FLASH MEMORIES ( NAND & NOR )
DMA |
Apply by Date | 06/11/2020 |
Applied Teams | 13 / 15 |
Duration | 6 months |
College | | 1. Jawaharlal Nehru University |
|
Tools-Technologies | C |
Mentor | Ganesan Narayanasamy |
Ganesan Narayanasamy's comments | The project has been successfuly completed |
Platform | 1 ) OpenPOWER/Power
|